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Dietmar Loy.
Time-Services Hardware Support in Fault-Tolerant Real-Time Systems,
Proceedings of the 5th international conference on VLSI and CAD
(ICVC´97), Seoul, Korea, October 13-15, 1997.
Abstract.
Designing a time service for distributed fault-tolerant real-time systems
based on packet networks requires to decide on the tradeoff between hardware
and software support. Aiming for a 1 µs precision and similar accuracy
measures in times of external UTC supply, this project focuses on the proper
hardware support and presents an implementation of a standard cell design
with the acronym UTCSU (Universal Time Coordinated Synchronization Unit).
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Klaus Schossmaier, Ulrich Schmid, Martin Horauer, Dietmar Loy.
Specification and Implementation of the Universal Time Coordinated
Synchronization Unit (UTCSU),
Journal of Real-Time Systems 12:3, May 1997.
download:
jrts12-3.ps (347KB),
jrts12-3.ps.gz (101KB)
(copyright KAP)
link:
JRTS
Abstract.
High-accuracy external clock synchronization can only be achieved with
adequate hardware support. We analyze the requirements and present the
specification and implementation of an ASIC running under the acronym
UTCSU dedicated to that purpose. It is built around an elaborated local
clock, which is based on an adder driven by a fixed-frequency oscillator.
This novel clock design allows a fine grained rate adjustability apt for
maintaining both local time with linear continuous amortization and
accuracy information as needed in interval-based clock synchronization.
Additional features incorporated in our UTCSU are facilities to timestamp
clock synchronization data packets, interfaces to couple GPS receivers,
some application support as well as sophisticated self-test machinery.
Apart from addressing design and engineering issues of the chip, we also
provide a basic programming model.
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Martin Horauer, Dietmar Loy.
UTCLIENT -- An ASIC Supporting Clock Synchronization in Distributed
Real-Time Systems,
Austrochip '97, Linz, Austria, April 9, 1997.
link:
Austrochip'97
Abstract.
This paper provides an overview of specification and implementation of
an ASIC running under the acronym UTCLIENT that supports external
clock synchronization by hardware.
It incorporates an adder-based clock to maintain local time,
facilities to timestamp packets containing synchronization data, interfaces
to GPS receivers and provides moderate application support.
This novel clock is distinguished by its fine grained rate adjustability
and hardware support for linear continuous amortization.
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Martin Horauer.
A Primer to Digital Design with Synopsys and Cadence,
TR 183/1-68, Technische Universität Wien, Dept. of Automation,
October 1996.
Contents.
1. SYNOPSYS - 1.1. Synopsys documentation - 1.2 Analyzing source files -
1.3 Directory hierarchy and file naming policy - 1.4 Simulation before synthesis -
1.5 Synthesis - 1.6 A design example -
2. Back-End design with CADENCE
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Klaus Schossmaier, Dietmar Loy.
An ASIC supporting External Clock Synchronization for Distributed
Real-Time Systems,
Proceedings of the 8th Euromicro Workshop on
Real-Time Systems, L'Aquila, Italy, June 12-14, 1996.
download:
euromicro96.ps (169KB),
euromicro96.ps.gz (50KB)
(copyright IEEE)
slides:
slides_utcsu.html
link:
Euromicro'96
Abstract.
Designing clock synchronization algorithms based on
packet networks for distributed real-time systems
requires to decide on the amount and functionality
of proper hardware support. Targeting a 1 µs precision
and similar accuracy measures in case of external UTC supply
from GPS receivers, this paper describes pertinent
features of a peripheral device called UTCSU manufactured as
an ASIC. The most salient ones are the introduction of an
adder-based clock, which allows a fine grained rate
adjustment, and maintenance of local accuracy intervals.
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Dietmar Loy.
GPS-Linked High Accuracy NTP Time Processor for Distributed
Fault-Tolerant Real-Time Systems,
PhD Thesis, Technische Universität Wien, Dept. of Computer Technology,
April 1996.
Abstract.
Designing a time service for distributed fault-tolerant real-time
systems based on packet networks requires to decide on the tradeoff
between hardware and software support. Targeting a 1 µs
precision and similar accuracy measures in case of external UTC
(Coordinated Universal Time) supply, this thesis concentrates on
the requirements of the proper hardware support and presents an
implementation of an ASIC with the acronym UTCSU (Universal
Time Coordinated Clock Synchronization Unit). All pertinent
features of the UTCSU are addressed. A novel adder-based clock,
adjustable in phase and frequency, maintains local time inside
the UTCSU. Drift and aging of the driving low-cost quartz
crystal oscillator is compensated by correction values obtained
from an clock synchronization algorithm. In addition to local
time, current clock accuracies are provided as asymmetric intervals
around the local clock. The time format used internally is an
extended version of the Internet Network Time Protocol (NTP)
format with 32 bits in the integer part and 59 bits in the
fractional part. Hardware support is provided for the programmed
insertion and deletion of leap seconds in the local clock. A
NTP-interface exports local time together with accuracy information
on primary output pins. A Synchronization Subnet Unit (SSU) can
timestamp each received and transmitted data packet on one
communication channel. Up to six SSUs are hosted in the UTCSU
which allows the design of a triple-redundant gateway node with
six independent network media connected to it. Three GPS Units
interface the one-pulse-per-second (1PPS) output of GPS
timing-receivers. UTCSU external application events are
timestamped through a 9-channel external input event recorder.
Comprehensive test and self-test logic enables the UTCSU to be
used in fault-tolerant real-time systems. Therefore every
single generated timestamp is protected by an 8-bit checksum.
Furthermore a sequence of timestamps can be compressed by either
a blocksum adder or a signature analysis register (SAR), and the
results compared with reference data, which are obtained from
the synchronous operation mode, where multiple UTCSUs run in
parallel. External events can be simulated internally during
power-up testing and during the system integration phase, which
makes the debugging phase easier. Snapshots of the current
state of the UTCSU can be taken at any given time.
The design followed a strict top-down design flow with a VHDL
RTL-description synthesized into a gate-level netlist followed
by back-end design for fabrication in a 0.7 µs CMOS standard
cell process. Scan-path as well as boundary-scan logic
according IEEE 1149.1 were inserted automatically.
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Klaus Schossmaier.
Dagstuhl Seminar 9611 on ``Time Services'', Report Nr.139,
March 11-15, 1996.
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Martin Horauer, Dietmar Loy.
Adder Synthesis,
Austrochip '95, Graz, Austria, 1995.
Abstract.
This paper describes the logic synthesis of several 91 bit wide
adders. Their performance is compared before and after synthesis
to tail out the power of a synthesis tool and to show the improvement
gained due to a more sophisticated structure. Therefore a breif
description of the investigated adder architectures is given.
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Klaus Schossmaier, Ulrich Schmid.
UTCSU Functional Specification,
TR 183/1-56, Technische Universität Wien, Dept. of Automation,
July 1995.
Abstract.
This report contains the final functional specification of the
Universal Time Coordinated (Clock) Synchronization Unit
(UTCSU) currently being developed as an ASIC at the Department
of Computer Technology. The UTCSU implements the bottom layers
of our novel Interval-Based Clock Validation (ICV)
technique that will furnish fault-tolerant distributed real-time
systems with local clocks synchronized to UTC with very high
accuracy. It is based on a number of inventive and unique features
devised by the authors, in particular an adder-based clock rate
and state correction and a similar accuracy interval
maintenance. Developed in the framework of our joint project
SynUTC, this document - actually several revisions emanated from
discussions with Dietmar Loy and Martin Horauer - forms one of
the major links between the research work of our groups.
